1. Field of the Invention
This invention relates to a method for fabricating a memory, and more particularly, to a method for fabricating a one time programmable read only memory (OTP-ROM).
2. Description of Related Art
The requirement for a memory is rising from day to day because microprocessors are becoming more powerful and software programs and computations are getting larger. Thus, it is a major task for the manufacturers of semiconductor devices to develop and fabricate high-capacity and economical memories to fulfill the market requirement. According to the basic read/write functions, memories are simply classified into two categories: read only memory (ROM) and random access memory (RAM). A ROM can only perform the reading task, but a RAM can perform both the reading and writing tasks. ROMs can be classified according to their method of data storing: mask ROM, programmable ROM (PROM), erasable programmable ROM (EPROM), and electrically erasable programmable ROM (EEPROM). On the other hand, RAMs can also be classified into the categories of static RAM (SRAM) and dynamic RAM (DRAM).
ROMs are widely used in mini-computers, microprocessor systems, and other digital devices for storing system information and the terminate and stay resident (TSR) programs such as BIOS. Since the fabrication of a ROM is very complicated, and includes numerous time-consuming processes and preparations for materials, the manufacturers normally code the needed programs and information from customers into memories within the fabrication process.
Since the rest of the structures, with the exception of the information stored during the programming process, are the same for most ROMs, ROMs are normally stocked semi-manufactured, at the stage before the programming process. After a specific program or information is given, the whole fabrication process of a ROM is quickly finished by patterning a mask and performing only the programming process. The foregoing method, which is a so-called post-programming mask-type ROM, is commonly used in industry.
A channel transistor is normally used as a memory cell in a ROM. Within the programming process, desired channel areas of a channel transistor are selectively implanted with dopants, such as boron, to change the threshold voltage to control the on/off of a memory cell. A ROM structure includes a polysilicon word line WL crossing a bit line BL, and the channels of the memory cells located at the regions between bit lines BL and beneath the word line WL. In a ROM, the stored binary data, 0 or 1, is dependent on whether or not the channel has ions implanted.
FIGS. 1A, 1B, and 1C are sectional diagrams showing a conventional fabrication process for a PROM, wherein FIGS. 1B and 1C have the same sectional direction, which is perpendicular to the sectional direction of FIG. 1A.
As shown in FIG. 1A, a substrate 10 is provided. The substrate 10 has a patterned memory cell area 9 and peripheral area. The peripheral area includes an NMOS active area 7 and a PMOS active area 8, and the PMOS active area 8 has an N well 11 formed on the substrate 10. A pad oxide layer (not shown) is then formed on the substrate 10 by a thermal oxidation process. A field oxide 14 is next formed on the substrate 10 by a local oxidation process to pattern an active area, and then the pad oxide layer is removed by a method such as a wet etching process. After that, an oxide layer 12 is formed on the surface of the active area by a thermal oxidation process. Then a polysilicon layer 16 is formed on the top of the oxide by a deposition process, such as a low-pressure chemical vapor deposition (LPCVD), wherein the polysilicon layer is then patterned by employing a photolithography and an etching processes.
A layer of inter-polysilicon dielectric material is formed on the top of the polysilicon layer 16 by a process such as a LPCVD process, and another layer of polysilicon is then formed on the top of the inter-polysilicon dielectric layer by a process such as a LPCVD process. A photolithography process and an etching process are performed to pattern and etch downward the layers of polysilicon and inter-polysilicon dielectric materials to form a polysilicon layer 20 and an inter-polysilicon dielectric layer 18. At the same time, a plurality of polysilicon layers 20 is formed on the peripheral area.
Referring to FIG. 1B, an etching process is performed to pattern the polysilicon layer 16 by using the polysilicon layer 20 as a mask. An n-type ion implantation process with a heavy concentration of ions is performed to form an ion implantation region 22 on the substrate 10 by using the polysilicon layer 20 as a mask in the memory cell, excluding the periphery area 7 and 8 that are covered by a mask. Another mask is used to cover the memory cell area 9 and the active area of the PMOS 8 for processing a conventional n-type ion implantation process to form an n-type ion implantation region of a light concentration 24 on the substrate of the active area of the NMOS 7. After removing the mask and using another mask to cover the memory cell area 9 and the active area of the NMOS 7, a conventional p-type ion implantation process is performed to form a p-type ion implantation region of a light concentration 26 on the substrate of the active area of the PMOS 8, and then the mask is removed.
Referring to FIG. 1C, an oxide layer is deposited to cover the semiconductor substrate and the structures thereon by using a method such as a LPCVD, and then an etching back process is performed to form spacers 28 of oxide on the sidewalls of the polysilicon layer 20 on the active areas of the NMOS 7 and the PMOS 8. This etching back process forms a spacer on the sidewalls of the polysilicon layer 20, dielectric layer 18, and polysilicon layer 16 as well.
Then, a conventional ion implantation process is performed to form a p-type ion implantation region of a heavy concentration 30 on the substrate of the active area of the PMOS 8 by using a mask covering the active area of the NMOS 7 and the memory cell 9, after which the mask is removed. Again, a conventional ion implantation process is performed to form an n-type ion implantation region of a heavy concentration 32 on the substrate of the active area of the NMOS 7 by using a mask covering the active area of the PMOS 8, and an n-type ion implantation region of a heavy concentration 34 on the substrate of the active area of the memory cell area.
The rest of the fabrication process for accomplishing an OTP-ROM that can be easily done by persons skilled in the art and is not described here.
The spacer structure 28 in a conventional PROM decreases the efficiency of programming. Even though the presence of the n-type ion implantation of a heavy concentration 22 can improve the efficiency of programming, the fabrication process becomes more complicated. Furthermore, the process of forming spacers in the memory cell area has to include etching back, which damages the field oxide and the polysilicon surface in the memory cell area, and further causes leakage current.